Balanced logical magnetic circuits



1960 A. J. MEYERHOIFF 2,925,500

BALANCED LOGICAL MAGNETIC' CIRCUITS Original Filed Dec. 51, 1954 2Sheets-Sheet 1 OUTPUT UTILIZATION CIRCUIT lNHlBlT I8 26 OUTPUT 40 Fl 6 2UTILIZATION CIRCUIT l2 llllOIOl O O O O COUNTER I6 FIG. 3 3 M OUTPUT "aUTILIZATION 2 CIRCUIT l5 z A' 7 A3 OUTPUT A UTILIZATION lllllll CIRCUITC 1 o I o o 1 COUNTER NVENTOR.

AL J. MEYERHOFF F [6.4

ATTORNEY United States Patent 2,925,500 BALANCED LOGICAL MAGNETICCIRCUITS Albert J. Meyerholf, Wynnewood, Pa., assignor to BurroughsCorporation, Detroit, Mich., a corporation of Michigan Originalapplication December 31, 1954, Serial No. 479,061, now Patent No.2,861,259, dated November 18, 1958. Divided and this applicationSeptember 8, 1958, Serial No. 759,775

7 Claims. (Cl. 307-88) This application is a division of my copendingapplication, Serial No. 479,061, filed December 31, 1954, for

fBalanced Logical Magnetic Circuits, now U.S. Patent No. 2,861,259,issued November 18, 1958.

This invention relates to bistable state magnetic storage devices andmore particularly to logical magnetic circuits incorporating a pluralityof interconnected magnetic storage devices.

Binary magnetic devices are well known and have been used for bothstorage and logical operations. In general magnetic cores are used whichpresent a rectangular hysteresis characteristic. In practice themagnetic cores are not truly rectangular, however. Such cores, afterbeing driven into magnetic saturation, return to a remanence conditionat a diflerent position upon the hysteresis curve. When driven from aremanence condition of one polarity into saturation of the samepolarity, the cores develop a small potential in windings thereabout.However, when the cores are switched from one rem'anence condition to anopposite saturation they develop a large potential in windings about thecores. Thus, the storage condition of the core may be interrogated bydriving it to saturation in a predetermined direction, and the potentialdeveloped at an output winding will be high or low depending upon theprevious core storage condition.

By combining several magnetic cores in a circuit, different logicaloperations may be performed. In general a sequence of storageinterrogation or shifting operations is produced to lodge the storedresult indicative of a predetermined logic in a particular core.Circuits for performing logic in this way have been heretoforedeveloped. However, because of the departure of the cores from truerectangular hysteresis characteristics, the logical circuits mustdiscriminate between the small and large potentials resulting whendifferent storage conditions are interrogated. The small potentialrepresents an undesired noise impulse which tends to limit thereliability of logical circuits. I

It is, accordingly, an object of the invention to provide improvedlogical magnetic circuits.

A more specific object of the invention is to improve the reliability oflogical magnetic circuits by decreasing their sensitivity to noiseimpulses.

In accordance with the present invention, therefore, logical circuitsare made less sensitive to noise impulses by introduction-of balancedcircuit techniques into bistable magnetic circuits. Thus, several coreshaving windings connected in a balanced circuit will produce equal andopposite noise impulses and may be coupled together in the mannerafforded by the invention to produce logical results.

One embodiment of the invention, therefore, comprises a balanced logiccircuit for performing the inhibit function. This circuit has a firstbistable magnetic element coupled to receive binary information. Asecond element is coupled to receive a conditioning signal, and atransfer circuitis provided for inhibiting the transfer of informationof one polarity from the first element to a third ele- 1 the samestorage state.

Patented Feb. 16, 1960 ment depending upon the state of the secondelement as determined by the presence or absence of the conditioningsignal.

A further logical circuit is provided as another embodiment of theinvention. This circuit includes four magnetic binary elements connectedwith input windings in two balanced circuit branches. Two ofthe elementswhich aid in the logical operations have equal and opposing windingsconnected in dilferent ones of the circuit branches. The other twoelements serve as input elements. Thus, as current is sent in a singledirection through the balanced circuit branches, any noise signals arebalanced out. Different types of logic may be performed by sequencing ofthe read-in and read-out signals at the different elements and thechoice of polarity of read-in and read-out excitation. For example, theEX- CLUSIVE OR logical function is performed in this type of circuit bypassing current commonly through the two branches and respectivewindings on the two input elements so that each input element will tendto arrive in The two logical elements have windings connected in eachbranch such that they tend to arrive at opposite storage states. Thus,if the input elements have like storage, the current in the two branchesis balanced and no change in storage state of the two logical elementsoccurs. If opposite storage states occur in the input elements, however,the current is unbalanced and one or the other of the logicalelementschanges states. Therefore, a change in storage state of eitherlogical element will indicate the existence of an EXCLU- SIVE ORrelationship of the signals stored in the input elements.

Other features and objects of the invention will be described throughoutthe following more detailed description of the invention and illustratedin the acompanying drawings, in which: i 1

Fig. 1 is a schematic diagram and accompanying truth table of a logicalinhibit circuit embodying the invention claimed in my prior copendingapplication, Serial No. 479,061, filed December 31, 1954, which issuedNovember 18, 1958, as U.S. Patent No. 2,861,259;

Fig. 2 is a schematic diagram and accompanying truth table of a logicalEXCLUSIVE OR circuit embodying the invention claimed in the presentdivisional application;

Fig. 3 is a schematic diagram together with accompanying truth table ofa counter circuit embodying the invention claimed in the presentdivisional application;

Fig. 4 is a schematic diagram together with the accompanying truth tableof a counter circuit embodying the invention claimed in my said priorcopending application, S.N. 479,061, filed December 31, 1954, whichissued November 18, 1958, as U.S. Patent No. 2,861,259;

Fig. 5 is a waveform diagram indicating operating conditions of thevarious illustrated embodiments of the invention; and

Figs. 6 and 7 are partial schematic diagrams illustrating optionalcircuit techniques for incorparation with circuits embodying theinvention.

Throughout the drawing like reference characters are used to identifysimilar features to facilitate comparison of the several figures. Inorder to more clearly point out the nature of the invention, those wellknown circuits which are used to obtain the necessary input signals anddriving current pulses are not illustrated. The necessary circuitoperating conditions are set forth however in connection withillustrative waveforms so that the invention and its mode of operationmay be clearly understood.

In order to follow the description of the invention more readily, thenotation and background material used in connection with the schematiccircuits is explained before proceeding with the detailed analysis ofthe difassumed that these represent'magnetic cores presentingrectangular hysteresis characteristics. Such cores tend to remain In aremanence condition of polarity l or after being driyen intocorresponding magnetic saturation.

' These materials and their characteristics are well known in the artand may be found described in such publications as the Transactions ofthe American Institute of Electrical Engineers for November 1953 in thearticle by Joseph Wylen entitled Pulse Response Characteristics ofRectangular-Hysteresis-Loop Ferromagnetic Materials.

Each of the magnetic cores is supplied with windings for producing amagnetic flux the ein in response to current flow. The dot notation isused to designatethe polarity of the windings. Thus, as current flowsinto a dotted winding terminal, the core will tend to store a 0.Conversely, if the current flows into an undotted winding terminal, thecore will tend to store a 1. The signals, storage conditions andcurrents are designated by'appropriate letters supplied with subscriptnumbers which designate a relative sequential time period. Thus Aindicatesthe signal arriving at element- A during the first time periodof a sequence of time periods. 'Likewise I indicates current flowing inthe second sequential me period.

NOT operation or an inversion of the signal or storage state.

' The inhibit function performed by the circuit of Fig. 1 is describedin the truth table it). Thus, input signals A and B may arrive in any ofthe four illustrated combinations to produce the output signal Crepresenting the inhibit function. By comparing the signals A, B and Cit is evident that when the signal A is 1 itcan only result in a signalof C equal to 1 when signal B is 0. Thus, when signal'A is l and alsosignal B is 1, signal C is 0. Accordingly, the signalB prevents thesignal A=1 from progressing to C and thus B may be termed the inhibitsignal.

Each of two input current signals arriving at windings 15 and 16respectively of cores A and B will, when present, establish a storagecondition. 1 during the first time sequence period. Considering togetherthe wave forms of Fig. 5 and the diagram of Fig. 1,.it is seen that thesignals A or B may be selectively derived fromthe periodic currentpulses 1 by any suitable logic or computer type circuitry. The nextsequential operation occurs during. a second sequential time period andthe current pulses 1 may be used directly. Athirdsequential step is usedto interrogate or shift-out the stored logical resultfrom the circuit.This shift operation may occur at either a further time period three asderived from the current 1 or may occur at the next succeeding timeperiod one as derived from 1 This latter operation is preferred where itis desired that only twotime periods be spent for completing. thelogical operation. However, to better separate the difierent logicalsteps throughout the ensuing description, the shift is designated tooccurduring the third time period of i The shift signal'SH may arrive atthe same time as the input signals A or B because of the balancedcircuit construction. The rectifiers 18 and 19 prevent current fromflowing in the loop L L, from potentials induced in any of the windings21, 22, 27 or 23. Thus, in the absence of current I signal transfercannot occur from one element to another, and therefore inhibitingcircuits are not necessary for preventing unwanted signal transfer fromone core to another in performance of the operations during time periodsother than that in which current 1 is flowing.

After the elements A and B have stored the incoming signals, the logicaltransfer to element C occurs by and 0 cu ren fla 2- fia-grrn terst tethrough two branch current paths I and I Diodes 18 and 19 are suppliedin each current path to assure that current flows in a single directionthrough the two branch paths, which direction is chosen depends upon theorientation of the diodes. A change in diode orientation may require acorresponding change in winding polarities for windings 21 and 22 aswell as for Windings 2'7 and 28. Thus, it is seen that the currententers the two windings 21 and 2.2 of element C so that equal andopposing flux is set up in element C when the paths are balanced forequal current flow. The resistors 25 and 2 6 serve to equalize anyslight unbalanced conditions caused by variations in circuit parameters.Each of the transfer windings 27 and 23 about the respective inputelements A and Bis connected to establish the same 0 storage state inresponse to current 1 Accordingly, when both elements A and B are in thesame storage state O() or 1-1, the current flow in branches 1,; equalsthe'current flow in branch T and the storage A' prirned notation Aindicated the logical V state of element C remains unchanged.

Whenever elements A or B are in the 1 state, the current 1 causes eitheror both of them to switch to the 0 state. This action is similar to theconventional interrogation or shift operation in reading out informationstored in magnetic bistable state element. However, in conventionalcircuits, and in each core A or B of this circuit, an unwanted noiseimpulse occurs in any core driven from the O remanence state to the 0saturation condition. In conventional circuits this noise is transmittedover the same signal path as the desired signal pulse of higheramplitude occurring when a l is stored in the element and it is drivento 0 saturation. With the present balanced circuit, however, it isevident that any noise impulse generated in element A is can celled oropposed by a similar noise impulse generated in element B so that thenet result due to current through windings 21 and 22 is the absence ofany noise transfer to element C. It has been observed that the balancecircuit of this invention is self balancing. That is, there is notendency for one element A to produce a different noise impulseamplitude or shape than the other element B, for any tendency to differis immediately opposed bythe inherent balancing action of'the circuit.The balanced circuit has also been found reliable over much greaterranges of'currents than tolerable with unbalanced circuits. This mayresult from a noise elimination device used to reduce noise in theunbalanced type of circuit, since such device in general is designed tocompensate for the noise at a particular current value. Accordingly, thebalanced circuits afforded by this invention 7 have been found to bemore reliable in operation than unbalanced circuits even when theyinclude noise reducing techniques. Now consider the inhibit logicproduced by circuit action of Fig. 1 under the various input signalconditions of Fig. 5. As the initial A signal 36 arrives along with theinitial B signal 31 both elements A and B are caused to remain in theirrespective storage states. Element C is in a 0 state because of priorread-out by the shift signal SH at either winding 23 or 29'. The shiftsignal is used to read the logical result from element C into the outpututilization circuit as by way of output winding 41. As indicated by therespective output signal waveform charts 44 and 45 of Fig. 5, read-outmay occur at either the first or third time periods. This isaccomplished by polarization of the readout winding 41 and diode 42 topass a signal only when the element C is switched from the l to that)storage state. Then either of the shift signals 81-1 or 8H5 may beemployed desired to restore element C to tr e 0 state and produce anoutput logical result when the element resides in the 1 state.

Theelement C resides unchanged in the 0 state in the presence of thesame storage state in both elements A an Breaks; fa slissuss tan fihsrssre Pre i a O read-out signal to the output circuit 40. This occurs forinput signal conditions 3031 or 36-37 as shown in Fig. 5. However, if Aand B contain different information 32-33, the state of element C isswitched to 1 by the resulting unbalanced current flow through windings21 and 22. Consider the input signals 3233 which place only element Ainthe 1 state. Since current in branch I will tend to switch element A tothe state, a higher switching voltage results in element A than inelement B so that greater current flows in branch I The resultinggreater current flow in winding 21 Will switch element C to the 1 stateso that the output signals 46 or 46' are produced in response tointerrogation of element C. Thus, since the inhibit signal B is missingthe 1 in element A is transferred to the output circuit 40.

Conversely, if the signals 34-35 exist, where only the inhibit signal Bis present, the switching of element B will cause more current to flowthrough winding 22 and cause element C to remain in its 0 state. Thus,the presence of inhibit signal B causes the O of signal A to remain a 0.Since when both elements A and B are 0, the element C remains 0, ashereinbefore explained, it is clear that the presence of a l at elementB inhibits the transfer of a 1 from element A to element C. The circuit,therefore, .performs the logical inhibit function with the attendantadvantages of high reliability afforded by the balanced current .paths.

The more complex EXCLUSIVE OR function of Fig. 2 is indicated in table11 by the column (C or D). The EXCLUSIVE OR circuit therefore serves toproduce output signals responsive to the presence of one and only onesignal at elements A and B. The inverse of the EX- CLUSIVE OR functionis the material equivalence function of column (C orD).

It is readily seen that the circuit of Fig. 2 is a balanced circuitwhich therefore affords the same reliable noisefree operationhereinbefore described. In order to produce the EXCLUSIVE OR function,the signals at both elements A and B must be inhibited by the signal atthe other element as may be seen by comparing the C and D signals ofchart 11 and noting that they'both represent the inhibit actionexplained in connection with Fig. 1. Accordingly, two inhibit circuitsare combined by supplying an additional element D similar to element Cwith balanced and opposing windings 50 and 51 but With windings 22 and50 or 21 and 51 in the same current branches connected in oppositesense. The same relationship, therefore, occurs with signals A, B and 0of chart 11 as existed in the chart 10 of Fig. l, and the circuitoperation of Figs. 1 and 2 in obtaining signal C is identical. Signal Dis derived in the same manner except that signals at element A inhibitthose at element B. The shift winding 52 of element D is actuatedsimultaneously with shift winding 29 of element C to produce in theseries windings 41 and 53 a single output signal (C or D) as shown inthe waveforms of Fig. 5. The signal appears at the output circuit 40 inresponse to switching of eitherelement C or D from the l to the 0 state.This occurs onlyjin the presence of a shift signal to develop asignal'in winding 41 or 53 of that polarity which will pass throughdiode 42.

A cycle of operation for Fig. 2 would include the reading in of signalsA and B into magnetic elements A and B, respectively, at time t In thetrivial case when A and B are 0, the interrogation current pulse 1 willsplit into two current paths I and I Element A will present the sameimpedance to current I as element B presents to current I so the currentflowing through winding 21 is substantially equal to that flowing inwinding 22, leaving element C in its 0 state. Similarly element Dremains in its 0 state during the presence of interrogating current L2.The application of shift pulses 5H to windings 29 and 52 will fail toproduce an output in output utilization circuit 40. In a similar manner,when both elements A'and B are'in their respective 1 states, currentpath I is impeded substantially the same as current path I is impeded sothat neither element C nor element D changes its magnetic remanentstate. Consequently When shift pulse 8H is applied to windings 29 and52, no output signal is transmitted to output utilization circuit '40.

When element A is switched to its 1 state by the presence of an A,signal but element B remains in its 0 state due to the absence of a Bsignal, the element A presents a higher impedance to current path I thanelement B presents to current path I so more current is available inbranch I than is available to branch I As a consequence element C isswitched to its 1 state and element D is merely driven further intonegative saturation and its 0 remanent state does not change. Theoccurrence of shifting pulse 5H will switch element C to its 0 state toproduce an output pulse across output winding 41. In a similar manner,when input signal B exists but input signal A is absent, current path Iis impeded more than current path I so that element D switches to its 1state and element C remains in its 0 state during the occurrence ofinterrogating current pulse 1;. When shift pulse 8H occurs,-itwill bethe switching element D that produces an output signal across winding 53for output utilization circuit 40. The circuit shown in Fig. 2 carriesout the EXCLUSIVE OR logic symbolically represented in the truth tableaccompanying Fig.2.

In order to produce the material equivalence function (C or D)'.whichrepresents two like input quantities 00 or l1,-the' EXCLUSIVE OR outputsignal is merely inverted. Circuits capable of inverting such signalsare well known in the art. The copending application of Robert W. Averyfor Logical Circuits filed December 4, 1952, Serial No. 324,118, now US.Patent No. 2,864,076 issued December 9, 1958, describes such invertingcircuits using magnetic cores. Thus it is seen that the balancedcircuits of this invention may serve as the basis for different types oflogical operation.

Another'circuit embodiment of the invention, as illus-v trated in Fig.3, is a binary counter. As seen from the truth table 12, when a seriesof input signals A is present, an output signal A occurs for very other1 input. Thus, the circuit provides at the output circuit 40, during thethird time period, signals developed by shift current 8H in the outputwinding 60. The output signals represent a reliable binary count derivedfrom randomly interspersed 0-1 signals A, arriving during the first timeperiod.

This binary counter circuit is an EXCLUSIVE OR circuit having a feedbackpath for providing the signals B from the EXCLUSIVE OR result excited ateither winding 41 or 53 in response to the shift current 8H Since thebinary count signal is'derivedsolely from element A, the separate outputwinding 60 is provided.' Consider the circuit operation of Fig. 3 whenthe signal sequence of 62 of Fig. 5 representing the input signal pulsesA is applied to winding 15 of magnetic element A. The first A signalpulse switches'element A to itsl state. Element 8' receives no inputpulse and remains in its 0 state. As was explained in connection withthe circuit operation of Fig. 2 when dissimilar inputs exist in elementsA and B, interrogation current I finds a different impedance to its flowthan current path I With element A in its 1 state and element B in its 0state, unbalanced current flow through windings 50 and 51 takes placeduring interrogation current pulse I causing element D to switch to its1 state and element C to remain in its 0 state. The subsequentapplication of a shift pulse to windings 29 and 52 of elements C and D,respectively, produces an output pulse D to the utilization circuit 40via winding 60. In addition, the switching voltage developed acrosswinding 53 of element D causes current pulse B to flow in a feedbackloop comprising winding 53, diode 42 and windings 16 and 41. Currentpulse B switches magnetic element B to its 1 state, but does not affectthe state of element C since the M.M.F. being applied to element Cbelieved descriptive of the nature of the invention in its various formsaretherefore described with particularity in the appended claims.

What is claimed is:

l. A circuit for performing the logical EXCLUSIVE OR function, saidcircuit comprising first, second, third and fourth magnetic cores eachcapable of assuming either of two stable states one of which is a setstate and the other a reset state; an input winding coupled to each ofsaid first and second cores for placing each core in said set state inresponse to an input signal applied to its respective input winding; asingle additional winding coupled to each of said firstand second cores,said additional winding functioning both as a read-out winding and as anoutput winding for its respective core; a first read-in winding coupledto each of said third and fourth cores; a second read-in winding coupledto each of said third and fourth cores; a first asymmetrical conductingdevice; a second asymmetrical conducting device; means for connecting ina first series path between first and second junction points saidfirst-core single additional winding, said first asymmetrical conductingdevice,:and said first read-in windings of said third and fourth cores;means connecting in a second series path between said first and secondjunction points, in parallel with said first series path, saidsecond-core single additional winding, said second asymmetricalconducting device, and said second read-in windings of said third andfourth cores, whereby a loop is formed'interconnecting all four of saidcores, said first and second asymmetrical conducting devices beingopposingly poled to prevent current flow around said loop; means forconnecting a voltage pulse source between said first and second junctionpoints for driving current through said first and second paths in thesame direction, said additional windings on said first and second coresbeing wound'in such sense that the said current driven therethroughtends to switch each of said first and second cores tosaid reset state,said first and second read-in windings of said third core being wound inopposite sense with respect to said current flow therethrough, saidfirst and second read-in windings of said fourth core being wound inopposite sense with respect to said current fiow therethrough, saidfirst read-in windings of said third and fourth cores being wound inopposite sense with respect to said current flow therethrough, saidsecond read-in windings of said third andfourth cores being wound inopposite sense with respect to said current flow therethrough; means forsimultaneously reading out said third and fourth cores; and output meansresponsive to the switching of either one of said third and fourth coreson read-out for'developing an output signal indicating that one or theother but not both of said first and second cores received an inputsignal.

2. A circuit for performing the EXCLUSIVE OR logical function, saidcircuit comprising: a pair of input magnetic cores each capable ofassuming either of two stable states of magnetic remanence, each inputcore having only two windings one of which functions as a read-inwinding and the other of which functions as a read-out winding';a' pairof output magnetic cores each capable of assuming either of two stablestates of magnetic remanence, eachoutput core having a pair of read-inwindings, a read-out winding and an output winding; means including afirst asymmetrical conducting device for connecting together in a firstseries path said read-out winding of ope'input core and one of saidread-in windings of each ofs aid output cores; means including a secondasymmetrical conducting device for connecting together in a secondseries path said read-out winding of the other input core and the otherread-in winding of each of said output cores; means for connecting saidfirst and second series paths together at first and second junctionpoints to form a loop interconnecting all four of said cores, saidfirst; and second asymmetrical conducting devices being opposingly'poled to prevent current flow around said loop; means for connecting avoltage pulse source between said first and second junction points fordriving current through said first and second series paths in the samedirection, said read-in windings of said input cores being similarlypoled with respect to the direction of said current, each of saidread-in windings on each of said output cores being opposingly poledwith respect to the other read-in winding on the same core and also withrespect to the read-in winding on the other output core which is in thesame series path; means for applying an input signal to the read-inwinding of said first core; means for applying an input signal to theread-in winding of said second core; means for simultaneously applyingread-out signals to the read-out windings of said output cores; andoutput means connected to said output windings of both output cores fordetecting the switching of either one of said output cores.

3. A circuit for performing a logical operation, said circuitcomprising: a pair of input magnetic cores each capable of assumingeither of two stable states of magnetic remanence, each input corehaving only two windings one of which functions'as a read-in winding andthe other of which functions as a read-out winding; a pair of outputmagnetic cores each capable of assuming either of two stable states ofmagnetic remanence, each output core having a pair of read-in windings,a readout winding and at least one output winding; means including afirst asymmetrical conducting device for connecting together in a firstseries path said read-out winding of one input core and one of saidread-in windings of each of said output cores; means including a secondasymmetrical conducting device for connecting together in a secondseries path said read-out winding of the other input core and the otherread-in winding of each of said output cores; means for connecting saidfirst and second series paths together at first and second junctionpoints to form a loop interconnecting all four of said cores, said firstand second asymmetrical conducting devices being opposingly poled'toprevent current flow around said loop; means for connecting a voltagepulse source between said first and second junction points for drivingcurrent through said first and second series paths in the samedirection, said read-in windings of said input cores being similarlypoled with respect to the direction of said current, web of said read-inwindings on each of said output cores being opposingly poled withrespect to the other read-in winding on the same core and also withrespect to the read-in winding on the other output core which is in thesame series path; means for applying an input signal to the read-inwinding of said first core; means for applying a signal to the read-inwinding of said second core; means for applying a read-out signal to theread-out winding of each of said output cores; and output circuit meansfor detecting the switching of one of said output cores.

4. Apparatus as claimed in claim 3 characterized in that said means forapplying a signal to the read-in winding of said second core comprises aconnection to an external signal source. 7

5. Apparatus as claimed in claim 3 characterized in that said means forapplying a signal to the read-in winding of said second core comprises afeedback circuit which includes in series the output winding on each ofsaid output cores.

6. A circuit for performing a logical operation, said circuit comprisinga pair of input magnetic cores each capable of assuming either of twostable states of magnetic remanence one of which is a reference state,each of said input cores having only an input winding and a read-outwinding; means connected individually to each of said input windings forselectively setting each core in the state other than said referencestate; a pair of output magnetic cores each capable of assuming eitherof two stable states of magnetic remanence, each of said output coreshaving at least a pair of read-in windings;

11 firstand second asymmetrical conducting devices; means for connectingin series in afirst branch path'the readout winding of one input core,said firstasymmetrical conducting device, and one of the read-inwindings'of each of said output cores; means for connecting in series ina second branch path the read-out winding of the other input core, saidsecond asymmetrical conducting device and the other read-in winding ofeach of said output cores; means for connecting the two ends of saidfirst and second branch paths together to form a loop, said first andsecond asymmetrical conducting devices being poled to inhibit currentflow around said loop; means connected to the said two ends of saidbranch paths for driving current in the same direction through each ofsaid branch paths, the read-out windings on said input cores being sowound that the said branch current thr'ethrough tends to switcheach'inp'ut core to its reference state, each winding of each pair ofread-in windings on each output core being so wound that equal andopposing magnetizing forces are applied to each output core, in responseto the cur'rent'which flows'throughthe branch paths when neither or bothof said input cores switch in response to such current flow and saidinput- 12 a core read-out windings present substantially equalimpedancesto said branch'currents, said read-in windings of'said-outputcores being so -wound thatwhen only one of said'input cores switches inresponse tovsaid' current flow then the magnetizing forces appliedtoeachoutput core by its respective pair of read-in windings are unequaland one only of said output cores thereupon is switched, according towhich of said inputcores switched; and means responsive to the switchingof either one of said output cores. 1

7. Apparatus as claimed in claim 6 characterized in that said meansresponsive to' the switching of either one of said outputcores'includes'means for feeding back the signal developed during-suchswitching to the read-in winding of oneionly'o'f said input cores, andadditional output means for detecting the switchingof a selected one ofsaid output coresg whereby said apparatus functionsas a1 binary counter.e

References Cited in the file of this patent ""furuTED' STATES PATENTS r2,741,758 Cray ..V. ..Y .V.' Apr. 10, 1 956

